The present invention relates to a comparator, and in particular to a comparator adapted to control the threshold voltage of an inverter. Furthermore, this invention relates to a voltage controlled oscillator circuit, and in particular to a voltage controlled oscillator circuit which oscillates at a high frequency.
Comparators are used in analog circuits such as VCO (voltage controlled oscillator circuits) forming PLL (phase-locked loops) which are used in portable radio devices and for clock frequency conversion. Recently, speed of analog circuits is increasing more and more. As a result, a short delay time and a high speed characteristic are required of comparators.
Voltage controlled oscillator circuits are used as components of PLL (phase-locked loops) used in portable radio devices and for clock frequency conversion. Sometimes the voltage controlled oscillator circuit incorporates two comparators. The oscillation frequency of the voltage controlled oscillator circuit is influenced by the delay time of the incorporated comparator. Accordingly, for obtaining a voltage controlled oscillator circuit having a high oscillation frequency, it is necessary to use a comparator which operates at high speed.
FIGS. 1, 2 and 3 shows circuit symbol, circuit, and output characteristic of a conventional comparator of inverter type, respectively. The conventional comparator 11 is formed of a CMOS inverter including a PMOS transistor Q1 and an NMOS transistor Q2. Input voltage Vin is input into gates of these transistors Q1 and Q2. Output voltage Vout is output from the drains of the transistors Q1 and Q2 connected in common.
This comparator 11 formed of the CMOS inverter has an operation delay time of a few nanoseconds, which is quite short, and therefore it operates at a high speed. Reference voltage of the comparator 11, i.e., a voltage serving as a reference voltage for comparing the magnitude of the input voltage is the threshold voltage of the transistors Q1 and Q2. When the input voltage Vin is lower than the threshold voltage Vth as shown in FIG. 3, the PMOS transistor Q1 turns on and consequently the output voltage Vout becomes xe2x80x9cHxe2x80x9d level which is relatively high in potential. On the other hand, when the input voltage Vin is higher than the threshold voltage Vth, NMOS transistor Q2 turns on and consequently the output voltage Vout becomes xe2x80x9cLxe2x80x9d level which is relatively low in potential.
FIGS. 4, 5 and 6 shows a circuit symbol, circuit, and output characteristic of a conventional differential comparator, respectively. This comparator 12 has a configuration obtained by combining a differential amplifier circuit with a single-ended amplifier circuit. The differential amplifier circuit includes PMOS transistors Q3 and Q4, NMOS transistors Q5 and Q6, and a current source 13. The single-ended amplifier circuit includes a PMOS transistor Q7 and an NMOS transistor Q8.
Gates of the NMOS transistors Q5 and Q6 are supplied with a reference voltage VR and an input voltage Vin, respectively. A drain output of the transistor Q6 is input into gates of the PMOS transistor Q7 and the NMOS transistor Q8. Output voltage Vout is output from the drains of the transistors Q7 and Q8 connected in common.
Since the differential amplifier circuit is used in this differential comparator 12, the input voltage Vin can be compared with the reference voltage VR accurately. In other words, when the input voltage Vin is lower than the reference voltage VR, then the drain output of the transistor Q6 is xe2x80x9cHxe2x80x9d level, the NMOS transistor Q8 turns on, and therefore the output voltage Vout becomes xe2x80x9cLxe2x80x9d level as shown in FIG. 6. On the other hand, when the input voltage Vin is higher than the reference voltage VR, then the drain output of the transistor Q6 is xe2x80x9cLxe2x80x9dlevel, the PMOS transistor Q7 turns on, and therefore the output voltage Vout becomes xe2x80x9cHxe2x80x9d level.
FIG. 7 is a circuit diagram of a conventional comparator of chopper type (hereinafter, comparator). This comparator includes inverter 14, capacitor 15, latch circuit 16, and first through third switches 17, 18 and 19. The first and second switches 17 and 18 are controlled by a clock signal "PHgr" so as to turn on/off. The third switch 19 is controlled by an inverted signal /"PHgr" of the clock signal "PHgr" (where xe2x80x9c/xe2x80x9d represents a bar indicating inversion) so as to turn on/off.
FIG. 8 is an operation timing diagram of the chopper comparator shown in FIG. 7. When the clock signal "PHgr" is xe2x80x9cHxe2x80x9d level (in other words, when /"PHgr" is xe2x80x9cLxe2x80x9d level), the first and second switches 17 and 18 turn on, resulting in auto zero operation. During the period when this auto zero operation is being carried out, voltages V1 and V2 respectively at nodes located on input and output sides of the inverter 14 become a threshold voltage Vth of the inverter, and a potential difference between this threshold voltage Vth and the reference voltage VR is stored in the capacitor 15.
When the clock signal "PHgr" is xe2x80x9cHxe2x80x9d level (in other words, when /"PHgr" is xe2x80x9cHxe2x80x9d level), the third switch 19 turns on and a comparison operation is performed. During the period when this comparison operation is being carried out, if the input voltage Vin is higher than the reference voltage VR then the output voltage V2 of the inverter 14 becomes xe2x80x9cLxe2x80x9d level. In synchronism with the next rising edge of the clock signal, this is output from the latch circuit 16 as an output voltage Vout of xe2x80x9cLxe2x80x9d level. On the other hand, during the period the comparison operation is being carried out, if the input voltage Vin is lower than the reference voltage VR then the output voltage V2 of the inverter 14 becomes xe2x80x9cHxe2x80x9d level. In synchronism with the next rising edge of the clock signal, this is output from the latch circuit 16 as an output voltage Vout of xe2x80x9cHxe2x80x9d level.
FIG. 9 is a circuit diagram of an oscillator circuit comprising two comparators. This oscillator circuit 2 includes first and second comparators 21a and 21b, capacitor 22 charged or discharged to supply a comparison voltage Vc to the first and second comparators 21a and 21b, first and second current sources 23a and 23b for charging or discharging the capacitor 22, first and second switches 24a and 24b and inverter 25 for respectively controlling on/off of the first and second current sources 23a and 23b, and latch circuit composed of two NAND gates 27a and 27b for latching a signal obtained by inverting an output signal of the first comparator 21a by means of inverter 26 and an output signal of the second comparator 21b and outputting an oscillation signal as an output voltage Vout.
The first comparator 21a is supplied with a voltage signal which is relatively high in potential (hereafter referred to as high reference voltage VRH) as a reference voltage. The second comparator 21b is supplied with a voltage signal which is relatively low in potential (hereafter referred to as low reference voltage VRL) as a reference voltage. The first switch 24a is controlled by the output signal of the latch circuit, i.e., the oscillation signal. The second switch 24b is controlled by a signal obtained by inverting the oscillation signal using the inverter 25.
FIG. 10 is an operation timing diagram of the oscillator circuit 2 shown in FIG. 9. When a terminal voltage VC, the voltage that increases due to charging, of the capacitor 22 exceeds the high reference voltage VRH, the first comparator 21a performs comparison operation after a delay time td. As a result, an output voltage of the inverter 26 (a voltage at a node A located on an output side of the inverter 26) supplied with an output signal of the comparator 21a is switched from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level. Accordingly, the latch circuit is reset, and the output voltage Vout of the latch circuit is switched from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
Furthermore, when the terminal voltage of the capacitor 22, i.e., the comparison voltage Vc is lowered due to discharging below the low reference voltage VRL, the second comparator 21b performs comparison operation after a delay time td. As a result, an output voltage of the comparator 21b (a voltage at a node B located on an output side of the comparator 21b) supplied with an output signal of the comparator 21a is switched from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level. Accordingly, the latch circuit is reset, and the output voltage Vout of the latch circuit is switched from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
FIG. 11 is a schematic diagram showing the configuration of a conventional voltage controlled oscillator circuit. This voltage controlled oscillator circuit includes first and second differential comparators 110 and 111, a capacitor 112 for supplying a comparison voltage Vc to the first and second comparators 110 and 111, first and second current sources 113 and 114 for charging or discharging the capacitor 112, converter circuit 115 for making each of the first and second current sources 113 and 114 generate a current proportionate to the input voltage, first and second switches 116 and 117 and inverter 118 for respectively controlling on/off of the first and second current sources 113 and 114, and latch circuit 119 for latching output signals of the first and second comparators 110 and 111 and outputting an oscillation signal of the voltage controlled oscillator circuit.
Voltage Vin is input into the converter circuit 115 as a control voltage input from the outside to control the oscillation frequency of the voltage controlled oscillation circuit shown in FIG. 11. The converter circuit 115 controls the first and second current sources 113 and 114, and makes each of the first and second current sources 113 and 114 to generate a current I proportionate to the input voltage Vin.
The first and second current sources 113 and 114 are driven on the basis of an output of the converter circuit 115 and generate the current I proportionate to the input voltage Vin. The positive terminal of the first current source 113 is connected to a power supply, and the negative terminal is connected to the first switch 116. The positive terminal of the second current source 114 is connected to the second switch 117, and the negative terminal is connected to the ground.
The first and second switches 116 and 117 are connected in series. Between the power supply terminal and the ground, therefore, the first current source 113, the first switch 116, the second switch 117, and the second current source 114 are connected in series.
The first switch 116 and the second switch 117 turn on/off on the basis of an output voltage Vout of the latch circuit 119, i.e., the oscillation signal of the voltage controlled oscillator circuit shown in FIG. 11. However, the first switch 116 and the second switch 117 are supplied with the oscillation signal of the voltage controlled oscillator circuit at phases shifted from each other by 180 degrees in order to prevent both the first switch 116 and the second switch 117 from turning on simultaneously, i.e., in order to make either the first switch 116 or the second switch 117 turn on exclusively. Precisely, for example, the oscillation signal of the voltage controlled oscillator circuit is input into the first switch 116 as it is, whereas the oscillation signal of the voltage controlled oscillator circuit is inverted by the inverter 118 and then input into the second switch 117.
A node between the first switch 116 and the second switch 117 is connected to one terminal of the capacitor 112, and further connected to non-inverting input terminals of the first and second comparators 110 and 111. Other terminal of the capacitor 112 is connected to the ground. Therefore, the current of the first current source 113 (when the first switch 116 is closed) charges the capacitor 112. A voltage Vc generated by this charging is applied to the non-inverting input terminals of the first and second comparators 110 and 111 as comparison voltage.
On the other hand, when the second switch 117 is closed, the capacitor 112 is discharged by the current dragged by the second current source 114. A voltage Vc generated by this discharging is applied to the non-inverting input terminals of the first and second comparators 110 and 111 as a comparison voltage.
The first comparator 110 is supplied with a reference voltage VRH which is relatively high in potential level (hereafter referred to as high reference voltage VRH) as an input signal of an inverting input terminal thereof. The first comparator 110 compares the high reference voltage VRH with the comparison voltage Vc. The output terminal of the first comparator 110 is connected to a reset terminal xe2x80x9cResetxe2x80x9d of the latch circuit 119.
The second comparator 111 is supplied with a reference voltage VRL which is relatively low in potential level (hereafter referred to as low reference voltage VRL) as an input signal of an inverting input terminal thereof. The second comparator 111 compares the low reference voltage VRL with the comparison voltage Vc. The output terminal of the second comparator 111 is connected to a set terminal xe2x80x9c/Setxe2x80x9d of the latch circuit 119. This set terminal xe2x80x9c/Setxe2x80x9d becomes effective when the input signal is at a relatively low potential level.
Operation of the voltage controlled oscillator circuit shown in FIG. 11 will now be described. FIG. 12 is a timing chart of the operation. In such a state that the first switch 116 is open (off) and the second switch 117 is closed (on), the second current source 114 draggers the current so that the capacitor 112 is discharged. Therefore, the terminal voltage of the capacitor 112, i.e., the comparison voltage Vc of the first and second comparators 110 and 111 gradually falls.
During this period, the output voltage of the first comparator 110 becomes a relatively low potential level (hereafter referredtoas xe2x80x9cLxe2x80x9dlevel), whereas the output voltage of the second comparator 111 becomes a relatively high potential level (hereafter referred to as xe2x80x9cHxe2x80x9d level). Therefore, the latch circuit 119 keeps its output voltage Vout, i.e., the oscillation signal of the voltage controlled circuit at xe2x80x9cLxe2x80x9d level which is the previous state. In FIG. 12, changes in the output voltages of the first and second comparators 110 and 111 are shown as voltage changes at the nodes A and B (output terminals of the first and second comparators 110 and 111) shown in FIG. 11.
When the comparison voltage Vc further falls and becomes equal to (at time T1) or less than the low reference voltage VRL, the output voltage of the second comparator 111 switches to xe2x80x9cLxe2x80x9d level. As a matter of fact, however, a delay is caused in the operation of the second comparator 111. Therefore, the output voltage of the second comparator 111 switches to xe2x80x9cLxe2x80x9dlevel when a delay time td has elapsed (at time T2) since the time when the comparison voltage Vc has become equal to or less than the low reference voltage VRL (at time T1).
At this time, the output voltage of the first comparator 110 remains at xe2x80x9cLxe2x80x9d level. Therefore, the latch circuit 119 is set, and the output voltage Vout of the latch circuit 119 switches to xe2x80x9cHxe2x80x9d level at time T2.
Since the output voltage Vout of the latch circuit 119 switches to xe2x80x9cHxe2x80x9d level, the second switch 117 turns off and the first switch 116 closes (turns on) at time T2. As a result, a current of the first current source 113 flows, and the capacitor 112 begins to be charged due to this current.
Therefore, the terminal voltage of the capacitor 112, i.e., the comparison voltage Vc of the first and second comparators 110 and 111 begins to rise. When the comparison voltage Vc exceeds the low reference voltage VRL (at time T3), the output voltage of the second comparator 111 switches to xe2x80x9cHxe2x80x9dlevel. As a matter of fact, however, a delay is caused in the operation of the second comparator 111. Therefore, the output voltage of the second comparator 111 switches to xe2x80x9cHxe2x80x9d level when a delay time td has elapsed (at time T4) since time T3.
At this time, the output voltage of the first comparator 110 remains at xe2x80x9cLxe2x80x9d level. Therefore, the latch circuit 119 keeps its output voltage Vout at xe2x80x9cHxe2x80x9d level. When the terminal voltage of the capacitor 112, i.e., the comparison voltage Vc further rises and exceeds the high reference voltage VRH (at time T5), the output voltage of the first comparator 110 switches to xe2x80x9cHxe2x80x9d level.
As a matter of fact, however, a delay is caused in the operation of the first comparator 110. Therefore, the output voltage of the first comparator 110 switches to xe2x80x9cHxe2x80x9d level when a delay time td has elapsed (at time T6) since time T5. At this time, the output voltage of the second comparator 111 remains at xe2x80x9cHxe2x80x9d level. Therefore, the latch circuit 119 is reset, and the output voltage Vout switches to xe2x80x9cLxe2x80x9d level at time T6.
Since the output voltage Vout of the latch circuit 119 switches to xe2x80x9cLxe2x80x9d level, the first switch 116 turns off and the second switch 117 closes (turns on) again at the time T6. As a result, the capacitor 112 begins to be discharged due to the current of the second current source 114. Therefore, the terminal voltage of the capacitor 112, i.e., the comparison voltage Vc of the first and second comparators 110 and 111 begins to fall.
When the comparison voltage Vc has become equal to or less than the high reference voltage VRH (at time T7), the output voltage of the comparator 110 switches to xe2x80x9cLxe2x80x9d level. As a matter of fact, however, a delay is caused in the operation of the first comparator 110. Therefore, the output voltage of the first comparator 110 switches to xe2x80x9cLxe2x80x9d level when a delay time td has elapsed (at time T8) since time T7.
At this time, the output voltage of the second comparator 111 remains at xe2x80x9cHxe2x80x9d level. Therefore, the latch circuit 119 keeps its output voltage Vout at xe2x80x9cLxe2x80x9d level. The voltage controlled oscillator circuit shown in FIG. 11 repeats such operation.
Assuming the change in the comparison voltage Vc per unit time xcex94t to be xcex94V, a period T of the voltage controlled oscillator circuit shown in FIG. 11 is represented by the following equation (1).
T={2xc2x7(VRHxe2x80x94VRL)/(xcex94V/xcex94t)}+4xc2x7tdxe2x80x83xe2x80x83(1)
Assuming the capacitance of the capacitor 112 to be C, and the current flowing through the first and second current sources 113 and 114 to be I, xcex94V/xcex94t in the equation (1) is represented by the following equation (2).
(xcex94V/xcex94t)=I/Cxe2x80x83xe2x80x83(2)
The converter circuit 115 makes the first and second current sources 113 and 114 let flow the current I proportionate to the input voltage Vin. Assuming the constant of proportionality between the input voltage Vin and the current I to be K, the current I is represented by the following equation (3). From the equation (3), therefore, the equation (2) can be rewritten as represented by the following equation (4). Finally, the equation (1) can be rewritten as represented by the following equation (5).
I=Kxc2x7Vinxe2x80x83xe2x80x83(3)
xcex94V/xcex94t=Kxc2x7Vin/Cxe2x80x83xe2x80x83(4)
T={2xc2x7(VRHxe2x88x92VRL)/(Kxc2x7Vin)}+4xc2x7tdxe2x80x83xe2x80x83(5)
For example, in the case of the oscillator circuit having the configuration shown in FIG. 9, it is necessary to perform comparison between the comparison voltage and the high and low reference voltages VRH and VRL accurately at high speed for generating a fast and accurate oscillation frequency. Furthermore, in the oscillator circuit 2, it is impossible to synchronize the timing when the comparison voltage Vc becomes equal to the high reference voltage VRH or low reference voltage VRL with an external clock.
The reason for this is as follows. When an external clock is used in the oscillator circuit 2, edges of the oscillation are synchronized to this clock. This results in inconvenience such as dispersion in oscillation periods or discontinuity in period setting. Therefore, in the oscillation circuit 2 having the configuration shown in FIG. 9, it is necessary that the first and second comparators 21a and 21b perform the comparison operation continuously.
In the conventional comparator of inverter type explained with reference to FIGS. 1 through 3, however, the threshold voltage determined by characteristics of the PMOS and NMOS transistors Q1 and Q2 serves as the reference voltage. This results in a problem that the reference voltage, i.e., the threshold voltage is extremely inaccurate because of factors such as dependence upon power supply voltage, dependence upon temperature, and dependence upon sampling. Therefore, it is difficult to perform accurate comparison operation using the conventional comparator of inverter type. Therefore, this comparator is inappropriate to the above described oscillation circuit.
Furthermore, in the conventional differential comparator explained with reference to FIGS. 4 through 6, its operation speed is restricted by the operation speed of the differential amplifier circuit. For example, in the case where the differential amplifier circuit has a CMOS configuration, therefore, the delay time becomes as long as several tens nanoseconds. Therefore, it is difficult to perform comparison operation at high speed using the conventional differential comparator. Therefore, this comparator is also inappropriate to the above described oscillation circuit.
Furthermore, in the conventional chopper comparator explained with reference to FIGS. 7 and 8, auto zero operation is performed during an interval of half a period of the clock signal "PHgr", and consequently the comparison operation cannot be performed during that interval. As a result, the conventional comparator of chopper type cannot be used when performing comparison in an a synchronous manner. Therefore, the conventional chopper comparator is also inappropriate to the above described oscillation circuit.
Furthermore, as represented by the equation (5), the period T of the voltage controlled oscillator circuit becomes longer than the original oscillation period by four times (4xc2x7td) the delay time td of the first and second comparators 110 and 111. In calculation, therefore, a maximum value of the oscillation frequency (reciprocal of the period T) of the voltage controlled oscillator circuit becomes a frequency represented by a reciprocal of 4xc2x7td.
The delay time td of a typical differential comparator is approximately 50 ns. In the conventional voltage controlled oscillator circuit, therefore, upper limit of its oscillation frequency is approximately 20 MHz in calculation. In the actual circuit design, therefore, the oscillation frequency must be suppressed to approximately 10 MHz. This frequency is insufficient for operating the voltage controlled oscillator circuit at high speed.
The present invention has been achieved in view of the above described problems. It is an object of the present invention to provide a comparator capable of performing fast and accurate comparison operations continuously. It is an another object of the present invention to provide a faster voltage controlled oscillator circuit capable by using a faster chopper comparator.
FIG. 13 is a diagram illustrating the principle of a comparator according to the present invention. This comparator 3 includes inverter 31, dummy inverter 32, and control circuit 33. The inverter 31 functions to compare input voltage Vin with the threshold voltage Vth serving as a reference voltage at the time of comparison, and output the output voltage Vout. The control circuit 33 functions to control the threshold voltages Vth of the inverter 31 and the dummy inverter 32.
The inverter 31 and the dummy inverter 32 are adapted to be controlled for their threshold voltage Vth by a Vth control voltage Vtc output from the control circuit 33. The inverter 31 and the dummy inverter 32 have the same configuration, and they are disposed in close vicinity to each other and are fabricated on the same semiconductor substrate by using the same process. Therefore, their electric characteristics, for example, their threshold voltages Vth can be regarded to be approximately equal.
The dummy inverter 32 is supplied with a Vth detecting input voltage Vinxe2x80x2 output from the control circuit 33. The dummy inverter 32 outputs a Vth detecting output voltage Voutxe2x80x2 to the control circuit 33. The control circuit 33 generates the Vth detecting input voltage Vinxe2x80x2 and outputs it to the dummy inverter 32. In addition, the control circuit 33 receives the Vth detecting output voltage Voutxe2x80x2 from the dummy inverter 32. The control circuit 33 is supplied with a reference voltage VR from outside.
Operation of the comparator 3 having the configuration as shown in FIG. 13 will now be described. The control circuit 33 supplies the Vth detecting input voltage Vinxe2x80x2 to the dummy inverter 32. The dummy inverter 32 outputs the Vth detecting output voltage Voutxe2x80x2 based on the Vth detecting input voltage Vinxe2x80x2 and the threshold voltage Vth. The control circuit 33 detects the threshold voltage Vth of the dummy inverter 32 based on the Vth detecting output voltage Voutxe2x80x2 and the Vth detecting input voltage Vinxe2x80x2.
The control circuit 33 compares in magnitude the detected threshold voltage Vth of the dummy inverter 32 with the reference voltage VR input from the outside. On the basis of a result of the comparison, the control circuit 33 adjusts a Vth control voltage Vtc so as to make the threshold voltage Vth of the dummy inverter 32, i.e., the threshold voltage Vth of the inverter 31 serving as a comparator coincide with the external reference voltage VR. The control circuit 33 outputs the Vth control voltage Vtc to the dummy inverter 32 and the inverter 31.
As a result, the threshold voltage Vth of the inverter 31 and the dummy inverter 32 becomes coincides with the fixed reference voltage VR. Therefore, it becomes possible to use the inverter 31 as a comparator for performing comparison operation at high precision. Furthermore, since the delay time of the inverter 31 is as small as a few nanoseconds, a faster comparator is realized. Furthermore, since the inverter 31 can operate continuously, it can be used also in the case where comparison is performed a synchronously.
The principle of the fact that the threshold voltage Vth of the inverter 31 and the dummy inverter 32 can be controlled using the Vth control voltage Vtc output from the control circuit 33 will now be described by referring to FIG. 14. As for the threshold voltage of an NMOS transistor (as well as a PMOS transistor), the threshold voltage Vthn of an NMOS transistor with respect to a reference voltage is a function of a back gate voltage VBn of the NMOS transistor, and it can be represented by the following equation (6).
Vthn (VBn)=Vthn+xcex94Vthn (VBn)xe2x80x83xe2x80x83(6)
The xcex94Vthn (VBn) in equation (6) is represented by the following equation (7). In equation (7), Kn and "PHgr"Fn are coefficients depending upon the fabrication process of the transistor or the temperature.
xcex94Vthn (VBn)=Kn ({square root over ( )}(2xc2x7"PHgr"Fnxe2x88x92VBn)xe2x88x92{square root over ( )}(2xc2x7"PHgr"Fn))xe2x80x83xe2x80x83(7)
Representing the threshold voltage of a PMOS transistor with respect to a substrate voltage by Vthp, a back gate voltage of the PMOS transistor by VBp, and the ratio of a current amplification factor xcex2n of the NMOS transistor to a current amplification factor xcex2p of the PMOS transistor by xcex2R (xcex2R=xcex2n/xcex2p), the threshold voltage Vth of the inverter is represented by the following equation (8). The VDD in equation (8) is a power supply voltage.
Vth=(VDDxe2x88x92|Vthp(VBn)|+Vthn(VBp)xc2x7{square root over ( )}xcex2R)/(1+{square root over ( )}xcex2R)xe2x80x83xe2x80x83(8)
From this equation (8), it will be understood that the threshold voltage of the inverter can be controlled by controlling the back gate voltage VBn of the NMOS transistor and/or the back gate voltage VBp of the PMOS transistor. In the present invention, therefore, the back gate voltage of the NMOS transistor and the PMOS transistor forming each of the inverter 31 and the dummy inverter 32 may be controlled in order to control the threshold voltage of the inverter 31 and the dummy inverter 32.
FIG. 22 is a schematic diagram showing a circuit configuration for description of a principle of a voltage controlled oscillator circuit according to the present invention. FIG. 23 is a timing chart illustrating operation of the voltage controlled oscillator circuit.
As shown in FIG. 22, a voltage controlled oscillator circuit according to the present invention includes two chopper comparators 120 and 121 (a first chopper comparator and a second chopper comparator), capacitor 122 for supplying a comparison voltage Vc to the two comparators 120 and 121, first and second current sources 123 and 124 for charging or discharging the capacitor 122, and converter circuit 125 for making the first and second current sources 123 and 124 generate a current I proportionate to input voltage Vin.
The voltage controlled oscillator circuit further includes first and second switches 126 and 127 and inverter 128 for controlling on/off of the first and second current sources 123 and 124. A logic circuit 129 latches the output signals of the first and second comparators 120 and 121, outputs the output voltage Vout that serves as an oscillation signal of the voltage controlled oscillator circuit according to the present invention, and generates clock signals "PHgr"1 and /"PHgr"1 (where /"PHgr"1 is an inverted signal of "PHgr"1) for switching operation of the first and second chopper comparators 120 and 121. This logic circuit 129 has a function of an output switching circuit.
The converter circuit 125 is supplied with, as its input voltage Vin, a control voltage input from the outside in order to control an oscillation frequency of a voltage controlled oscillator circuit according to the present invention. The converter circuit 125 controls the first and second current sources 123 and 124, and makes each of the first and second current sources 123 and 124 to generate a current I proportionate to the input voltage Vin.
The first and second current sources 123 and 124 are driven on the basis of an output of the converter circuit 125 and generate the current I proportionate to the input voltage Vin. The positive terminal of the first current source 123 is connected to a power supply terminal, and the negative terminal is connected to the first switch 126. The positive terminal of the second current source 124 is connected to the second switch 127, and the negative terminal is connected to the ground.
The first and second switches 126 and 127 are connected in series. Between the power supply terminal and the ground, therefore, the first current source 123, the first switch 126, the second switch 127, and the second current source 124 are connected in series.
The first switch 126 and the second switch 127 turn on/off on the basis of an output voltage Vout of the logic circuit 129, i.e., the oscillation signal of the voltage controlled oscillator circuit according to the present invention. However, the first switch 126 and the second switch 127 are supplied with an input signal for their on/off control, i.e., the oscillation signal of the voltage controlled oscillator circuit at phases shifted from each other by 180 degrees in order to prevent both the first switch 126 and the second switch 127 from turning on simultaneously, i.e., in order to make either the first switch 126 or the second switch 127 turn on exclusively.
Precisely, for example, the oscillation signal of the voltage controlled oscillator circuit is input into the first switch 126 as it is, whereas the oscillation signal of the voltage controlled oscillator circuit is inverted by the inverter 128 and then input into the second switch 127.
A node between the first switch 126 and the second switch 127 is connected to one terminal of the capacitor 122, and further connected to non-inverting input terminals of the first and second comparators 120 and 121.
Other terminal of the capacitor 122 is connected to the ground. When the first switch 126 is closed (on), therefore, the capacitor 122 is charged due to the current of the first current source 123. A voltage Vc generated by this charging is applied to the first and second comparators 120 and 121 as a comparison voltage. On the other hand, when the second switch 127 is closed (on), the capacitor 122 is discharged due to the current dragged by the second current source 124. A voltage Vc generated by this discharging is applied to the first and second comparators 120 and 121 as a comparison voltage.
The first and second chopper comparators 120 and 121 are adapted to be alternately switched from a comparison operation state to an auto zero state and vice versa by the clock signals "PHgr"1 and /"PHgr"1. For example, when the clock signal "PHgr"1 is xe2x80x9cHxe2x80x9d level, the first comparator 120 supplied with a reference voltage VRH which is relatively high in potential level performs comparison operation. On the other hand, the second comparator 121 supplied with a reference voltage VRL which is relatively low in potential level is in the auto zero state.
In this state, the first switch 126 is closed and the second switch 127 is open. As a result, the capacitor 122 is charged. Therefore, the terminal voltage of the capacitor 122, i.e., the comparison voltage Vc of the first and second comparators 120 and 121 gradually rises. Therefore, it is sufficient that the first comparator 120 having the reference voltage VRH compares the comparison voltage Vc with the threshold voltage VRH. Thus, even if the second comparator 121 having the reference voltage VRL is in the auto zero state, there occurs no inconvenience at all.
In contrast with this, when the clock signal "PHgr"1 is xe2x80x9cLxe2x80x9d level, the first comparator 120 supplied with the reference voltage VRH is in the auto zero state. On the other hand, the second comparator 121 supplied with the reference voltage VRL performs comparison operation. In this state, the first switch 126 is open (off) and the second switch 127 is closed (on). As a result, the capacitor 122 is discharged. Therefore, the terminal voltage of the capacitor 122, i.e., the comparison voltage Vc of the first and second comparators 120 and 121 gradually falls.
Therefore, it is sufficient that the second comparator 121 having the reference voltage VRL compares the comparison voltage Vc with the threshold voltage VRL. Thus, even if the first comparator 120 having the reference voltage VRH is in the auto zero state, there occurs no inconvenience at all.
The logic circuit 129 incorporates a latch circuit for latching the output signals of the first and second comparators 120 and 121. This latch circuit is not illustrated. In addition, the logic circuit 129 incorporates a clock signal generation circuit for generating the clock signals "PHgr"1 and /"PHgr"1. This clock signal generation circuit is also not illustrated. The clock signal generation circuit generates the clock signal "PHgr"1 in synchronism with and with a slight delay as compared with an output voltage Vout of the logic circuit 129, i.e., the oscillation signal of the voltage controlled oscillator circuit according to the present invention. The clock signal generation circuit supplies this clock signal "PHgr"1 to the first comparator 120 having the reference voltage VRH.
Furthermore, the clock signal generation circuit shifts the phase of the clock signal "PHgr"1 by 180 degrees and supplies the resultant clock signal to the second comparator 121 having the reference voltage VRL. Therefore, the clock signal generation circuit of the logic circuit 129 has a function of a delay circuit for delaying the output voltage Vout of the logic circuit 129 by a predetermined time and outputting the delayed signal.
Operation of the voltage controlled oscillator circuit shown in FIG. 22 will now be described by referring to FIG. 23. In such a state that the first switch 126 is open (off) and the second switch 127 is closed (on), the second current source 124 drags the current so that the capacitor 122 is discharged. Therefore, the terminal voltage of the capacitor 122, i.e., the comparison voltage Vc of the second comparator 121 gradually falls.
In this state, the second comparator 121 having the reference voltage VRL performs the comparison operation, whereas the first comparator 120 having the reference voltage VRH is in the auto zero state. The output voltage of the second comparator 121 is xe2x80x9cHxe2x80x9d level, and the output voltage Vout of the logic circuit 129 becomes xe2x80x9cLxe2x80x9d level. In FIG. 23, changes in the output voltages of the first and second comparators 120 and 121 are shown as voltage changes at nodes A and B (output terminals of the first and second comparators 120 and 121) shown in FIG. 22.
When the comparison voltage Vc further falls and becomes equal to or less than the low reference voltage VRL (at time T11) and a delay time caused by the second comparator 121 has elapsed (at time T12), then the output voltage of the second comparator 121 switches to xe2x80x9cLxe2x80x9d level. Therefore, the output voltage Vout of the logic circuit 129 switches to xe2x80x9cHxe2x80x9d level at time T12.
Since the output voltage Vout of the logic circuit 129 switches to xe2x80x9cHxe2x80x9d level, the second switch 127 turns off and the first switch 126 closes (turns on) at time T12. As a result, a current from the first current source 123 flows, and the capacitor 122 begins to be charged by this current.
Therefore, the terminal voltage of the capacitor 122, i.e., the comparison voltage Vc of the first comparator 120 begins to rise. In this state, the first comparator 120 having the reference voltage VRH performs the comparison operation, whereas the second comparator 121 having the reference voltage VRL is in the auto zero state. The output voltage of the first comparator 120 is xe2x80x9cLxe2x80x9d level, and the output voltage Vout of the logic circuit 129 is xe2x80x9cHxe2x80x9d level.
When the terminal voltage of the capacitor 122, i.e., the comparison voltage Vc further rises and exceeds the high reference voltage VRH (at time T13), and a delay time caused by the first comparator 120 has elapsed (at time T14), then the output voltage of the first comparator 120 switches to xe2x80x9cHxe2x80x9d level. Therefore, the output voltage Vout of the logic circuit 129 switches to xe2x80x9cLxe2x80x9d level at time T14.
Since the output voltage Vout of the logic circuit 129 switches to xe2x80x9cLxe2x80x9d level, the first switch 126 turns off and the second switch 127 closes (turns on) also at time T14. As a result, the capacitor 122 begins to be discharge again.
Therefore, the terminal voltage of the capacitor 122, i.e., the comparison voltage Vc of the second comparator 121 begins to fall again. The first comparator 120 having the reference voltage VRH is brought into the auto zero state, whereas the second comparator 121 having the reference voltage VRL performs the comparison operation. The output voltage of the second comparator 121 is kept at xe2x80x9cHxe2x80x9d level, and the output voltage Vout of the logic circuit 129 is xe2x80x9cLxe2x80x9d level. The voltage controlled oscillator circuit shown in FIG. 22 repeats such operation.
Thus, in the present invention, the comparison between the comparison voltage based upon the control voltage for controlling the oscillation frequency of the voltage controlled oscillation circuit and the reference voltage is performed by the faster chopper comparator. As a result, the voltage controlled oscillator circuit can operate at higher speed.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.